Job Description:

We are seeking a skilled and motivated Performance and Power (PnP) Modeling Engineer to lead modeling, analysis, and optimization efforts across the full silicon development lifecycle. This role spans architectural modeling, RTL-level analysis, gate-level estimation, and post-silicon correlation. You will build infrastructure, analyze real workloads, identify inefficiencies, and collaborate across hardware and software teams to deliver high-performance and energy-efficient CPU designs. ​

Responsibilities

• Define and simulate key CPU workloads (boot, idle, burst, sustained) to identify architectural bottlenecks and drive data-backed design decisions.
• Construct tradeoff models and generate performance vs. power curves to support architectural optimization.
• Implement RTL-level power estimation flows using tools such as PowerPro, Joules, or RTLA.
• Analyze switching activity (VCD/SAIF), identify high-power hotspots, and drive RTL improvements including clock gating and logic isolation.
• Establish and maintain DV test suites and microbenchmarks for PnP scenarios.
• Integrate power/performance tests into DV regression infrastructure to track trends over time.
• Build gate-level power flows and dashboards to track regression trends and physical power characteristics.
• Correlate pre-silicon projections with post-silicon results using on-chip sensors, PMUs, and DVFS sweep data.
• Work cross-functionally with architecture, RTL, physical design, validation, and firmware teams to drive design efficiency.

Minimum Qualifications:​

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of experience in CPU-focused performance and/or power modeling.
• Strong understanding of CPU microarchitecture: pipeline, cache, memory systems, control logic, and interconnect paths.
• Experience with power analysis tools and switching activity formats (VCD, SAIF, FSDB).
• Familiarity with RTL design and power estimation workflows.
• Exposure to DV regression infrastructure and simulation pipelines.​

​Preferred Qualifications:

• Experience building power-aware microbenchmarks for architectural validation.
• Background in RTL power reduction techniques (clock gating, signal isolation, logic pruning).
• Experience analyzing gate-level power and correlating it with RTL-level projections.
• Familiarity with post-silicon measurement infrastructure and silicon data extraction (PMUs, voltage/current rails, thermal sensors).
• Solid scripting and automation skills (e.g., shell, Python, git-based workflows).