Responsibilities

• Define and document system-level architecture, data flows, memory maps, and transaction models for high-performance computing systems; specify NoC topology, power domains, clock domains, and interface requirements.
• Define how the product is partitioned across dies, the die-to-die topology, and how memory is provisioned across the package.
• Build and extend system-level performance models to evaluate partitioning options, die-to-die topology, memory provisioning and package composition.
• Run workload-driven analysis to set credible targets and test whether architectural choices meet them.
• Quantify what crosses the die boundary for a given partitioning, and what that costs in bandwidth, latency and power.
• Correlate architectural models against detailed microarchitectural models, and both against RTL, so projections can be trusted.
• Own the correlation methodology and the regression infrastructure that keeps it honest as the design moves.
• Diagnose divergence between model and implementation and drive it to root cause.
• Turn model output into architectural recommendations, with the assumptions and sensitivities stated.
• Coordinate delivery and integration of internal and external IP, including interconnects such as PCIe, DDR, HBM, and AMBA CHI NoC.
• Work with foundry and design service partners on SOW definition and technical deliverable management.
• Define and drive PPA targets at chip, subsystem, and IP levels.
• Collaborate with firmware, software, and verification teams on functional and PPA requirements.
• Represent architecture decisions across teams, and mentor other engineers as the role grows.

Qualifications & Skills

• Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 6+ years in SoC or ASIC architecture, design or integration, or in system-level performance modelling.
• Strong knowledge of SoC architecture and design principles.
• Experience documenting system-level architecture requirements.
• Experience with on-chip interconnect protocols and architectures.
• Demonstrated experience building or substantially extending performance models used to make real design decisions.
• Proficiency in C++ and Python for modelling, analysis and automation.
• Ability to present a quantitative argument clearly enough to change an architectural decision.
• Strong written and verbal communication, and the ability to lead vendor discussions.

Preferred Qualifications & Skills

• RISC-V or Arm CPU architecture, including cache and memory hierarchy design.
• AMBA CHI network-on-chip, and system-level cache behaviour.
• Advanced packaging: 2.5D and 3D integration, chiplet architectures, and die-to-die interfaces such as UCIe, BoW and CoWoS, including partitioning and floorplan trade-offs.
• Experience correlating a performance model against RTL on a program that reached silicon.
• LPDDR or HBM memory subsystem modelling — scheduling, page policy, bank and rank parallelism.
• Workload characterisation methodology, including reuse-distance and roofline analysis.
• Foundry ecosystem familiarity, including scaling behaviour across node transitions.
• PCIe, UCIe, DDR/LPDDR and HBM.
• High-performance or server-class CPU experience.

What We Offer

• Lead impactful architecture decisions shaping next-generation heterogeneous computing
• Competitive compensation & benefits package
• Collaboration with talented engineers passionate about cutting-edge CPU technologies.
• Opportunities for professional growth in an innovative, fast-paced environment
• A flexible and inclusive work culture